λ-scaled Mead–Conway style rules, illustrative only — not a specific fabricated PDK. Click any component in the 3D view (or the schematic, or the tree) to see its own dimensions in the Property Inspector.
CMOS INVERTER — SCHEMATIC · click any terminal, gate or net to locate it in the 3D layout · bubble on gate = PMOS (P-channel)
X — source · drain axis
Y — process layer stack
Z — PMOS (N‑well) / NMOS (substrate)
CMOS INVERTER
Vertical dimensions are exaggerated for visualization; this is a conceptual CMOS layout, not a fabrication-ready PDK layout. Dimensions, spacing and layer thicknesses are not design-rule compliant — topology and functional relationships are physically meaningful.
IN0
PMOSON
NMOSOFF
OUT1
Logical/behavioral visualization — not a transistor-level physical simulation.
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🎙️AI VOICE TUTORbulbul:v4-flash
CONTEXTNone (Full Layout)
IN=OFF → HIGH-Z / FLOATING
AI Tutor Ready
Sarvam AI Tutor
Welcome to the CMOS AI Voice Tutor! Ask any question about VLSI layout, lambda design rules, or transistor physics. Click any layer in 3D to ask contextual questions in English, Hindi, or Telugu.
PROPERTY INSPECTOR
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Select a layer, region, or tree node to inspect its function, electrical role, and physical relationships.
ARCHITECTURE TREE
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